1. Field of the Invention
The present invention relates in general to non-volatile memories. More particularly, the present invention relates to non-volatile memories in which an embedded algorithm executed from a ROM is required.
2. The Prior Art
Current flash memories execute embedded algorithms to handle all modify operations. All these operations have become increasingly complex both because the number of allowed operations have been increased and because technology problems require very complex flows of digital and analog operations to be managed by an embedded microcontroller.
It is possible to check a lot of single circuitry functionality on a prototype chip, but usually the algorithm flows can only be verified in the on-chip implemented version. It is not possible to change these flows because the microcontroller executes instructions from a read-only memory (ROM) and a change to one or more masks is needed to change the stored code.
Current flash memories have a great complexity and the embedded algorithm has to execute numerous tasks such as factory programming, enhanced factory programming, non-volatile protection of sectors, etc. In particular there are multi-level devices that require very complex algorithms. The fact that process evolution has become increasingly faster causes great variations in technology parameters. Subsequent changes in parameters such as the applied voltages and timing during modify operations are required in order to match the technological requirements. All these issues necessitate changes in the algorithm flow. These changes may occur more than one time from first prototype chip to the final production of the device, and often the changes must be directly checked on silicon.
All modify operations in a flash memory device are obtained by applying well-defined voltage values to selected and not selected memory cells. These voltages are different accordingly to each operation and must be applied for timings that depend on the specific technology. Each modify operation employs a very high number of sequences that in the latest-generation devices requires several thousands of instructions. Usually a microcontroller decodes and executes the right sequence of instructions for the operation required from the user. All these instructions are usually stored in a ROM (Read Only Memory) that has both the advantages of a low area occupation and of a non-volatile memory. The memory that stores algorithm instructions has to be non-volatile because the flow has to be available after the power on of the device. Even if a dedicated flash area could be used to store the algorithm, this would require a high area cost and would not allow a fast access to execute the algorithm since reading from a ROM is much faster than from flash cells. On the other hand, the great disadvantage of using a ROM to store the algorithm instructions is the need of a mask set request in order to modify any flow, as previously explained.
It is sometimes necessary to modify an algorithm in order to correct design bugs. The algorithm flow is fixed in the prototype chip in an embedded ROM by a VIA mask. It is not possible to change these flows without at least a new mask release. If, for instance, there is a bug in a specific flow, the right correction can be only simulated but a mask request is needed in order to check the real behavior of the modifications on the new silicon.
In one possible approach to address the problem, programmable fuses are used in order to create the option to alter critical circuits, to match some ill-defined technology parameters. A first disadvantage is the high area cost because options are programmable fuses that by their nature require a particular array organization and dedicated algorithm to be programmed and erased. Another disadvantage is that with this method the variables—and their ranges that can be changed via fuses—should be known and hence fixed before first prototype chip is out. Obviously, possible bugs cannot be known before they appear, so in some cases the fuses could not be able to correct these bugs or could not help in finding a different solution to problems that arise.
Another possible approach consists in introducing an embedded RAM that could be used during testing operations instead of the embedded ROM, in order to check each flow modification. Once the optimal code has been found, it could be implemented by one definitive mask that allows changing the on-chip ROM. The disadvantage of this approach is in terms of area since a RAM core is introduced with the related cells needed for decoding during read and write access. Moreover, new routines to manage the RAM controller must be introduced in the existent algorithm.
FIG. 1 is a diagram showing the architecture for a typical prior-art flash memory. The microcontroller 10 executes instructions from ROM 12 and controls all the circuitry for voltage generation and management in voltage generator 14 and address decoding for row decoder 16 and column decoder 18 coupled to memory array 20. Output data from the memory array 20 is presented by output buffers 22. Moreover, information concerning timings, fails, and attempts is stored in dedicated digital circuitry 24.
The particular code that has to be executed depends on the command issued by the user and interpreted by the Command User Interface (CUI) 26. The T-latch block 28 in FIG. 1 includes a group of dedicated latches (t-latches) used only during the tests of the device whether to check the functionality of some circuitry or to execute some operations not accessible by the user. A well-defined command sequence (not known by the user) is provided to the CUI 26 to set these t-latches.
The CUI 26 sends commands to the microcontroller 10. To execute the commands, the microcontroller sends selection signals to digital circuitry 24 and voltage generator 14 and receives query signals from digital circuitry 24. The digital circuitry 24 sends decoding signals to the row decoder 16 and column decoder 18 to select cells for testing or for user-mode standard operations such as read, program, and erase.
FIG. 2 is a diagram illustrating the matrix organization and decoding of instructions from a prior-art ROM such as ROM 12 shown in FIG. 1. In an exemplary ROM 12 storing 1,024 instructions, the instructions available to the microcontroller 10 of FIG. 1 are stored in the ROM matrix array 20, organized in 64 rows and 256 columns. As is well understood by persons of ordinary skill in the art, each instruction is read by using row decoder 16 to select one row (by activating the corresponding ROW_SEL signal) and using column decoder 18 to select a group of sixteen columns (a word) from among the 256 available (by activating the corresponding COL_SEL signal). The ROM address (ROM_ADD) is a 10-bit bus in which four lines (ROM_ADD<3:0>) decode the selected group of sixteen of the column lines (COL_SEL<15:0>) while the other six lines (ROM_ADD<9:4>) decode the selected one of the row lines (ROW_SEL<63:0>).